1. Field of the Invention
The present invention relates to an electronic device structure. In particular, the present invention relates to an active matrix electronic device having a thin film transistor (TFT) formed on an insulating body, and to a method of driving an active matrix electronic device.
2. Description of the Related Art
EL displays (also referred to as electroluminescence displays) have been gathering attention in recent years as flat panel displays, which are substitutes for LCDs (liquid crystal displays), and research into such displays is proceeding apace.
LCDs can roughly be divided into two types of driving methods. One is a passive matrix type used in an LCD such as an STN-LCD, and the other is an active matrix type used in an LCD such as a TFT-LCD. EL displays can also be similarly broken down roughly into two types. One is a passive matrix type, and the other is an active matrix type.
For the passive matrix type, wirings which become electrodes are arranged in portions above and below EL elements (also referred to as electroluminescence elements). Voltages are applied to the wirings in order, and the EL elements turn on due to the flow of an electric current. On the other hand, each pixel has a thin film transistor with the active matrix type, and a signal can be stored within each pixel.
A schematic diagram of an active EL display device is shown in FIGS. 13A and 13B. FIG. 13A is a schematic diagram of an entire circuit, and a substrate 1350 has a pixel portion 1353 in its center. Gate signal line driver circuits 1352 for controlling gate signal lines are arranged to the left and right of the pixel portion. The arrangement may also be on only one side, left or right, but considering such issues as operational efficiency and reliability, it is preferable to use both positions as shown in FIG. 13A. A source signal line driver circuit 1351 for controlling source signal lines is arranged above the pixel portion. One pixel portion circuit in the pixel portion 1353 of FIG. 13A is shown in FIG. 13B. Reference numeral 1301 denotes a TFT which functions as a switching element during write in to the pixel (hereafter referred to as a switching TFT) in FIG. 13B. Reference numeral 1302 denotes a TFT which functions as an element (electric current control element) for controlling electric current supplied to EL elements 1303 (hereafter referred to as an EL driver TFT). The EL driver TFT 1302 is arranged between an anode of the EL element 1303 and an electric current supply line 1307 in FIG. 13B. It is also possible, as a separate structuring method to arrange the EL driver TFT 1302 between a cathode of the EL element 1303 and a cathode electrode 1308. However, from the fact that it is good for TFT operation to have a source region connected to ground, and from limitations on the manufacture of the EL elements 1303, a method in which a p-channel TFT is used in the EL driver TFT 1302 and is arranged between the anode of the EL element 1303 and the electric current supply line 1307 is generally seen and often employed. Reference numeral 1304 denotes a storage capacitor for storing a signal (voltage) input from a source signal line 1306. One terminal of the storage capacitor 1304 is connected to the electric current supply line 1307 in FIG. 13B, but a specialized wiring may also be used. A gate electrode of the switching TFT 1301 is connected to a gate signal line 1305, and a source region of the switching TFT 1301 is connected to the source signal line 1306. Further, a drain region of the EL driver TFT 1302 is connected to an anode 1309 of the EL element 1303, and a source region of the EL driver TFT 1302 is connected to the electric current supply line 1307.
The EL element has a layer (hereafter referred to as an EL layer) containing an organic compound in which electroluminescence (luminescence generated by the addition of an electric field) is obtained, an anode, and a cathode. As to the luminescence in the organic compound, there is emission of light when returning to a ground state from a singlet excitation state (fluorescence), and emission of light when returning to a ground state from a triplet excitation state (phosphorescence), and the electronic device of the present invention may use both types of light emission.
Note that all layers formed between the anode and the cathode are defined as EL layers in this specification. Specifically, layers such as a light emitting layer, a hole injecting layer, an electron injecting layer, a hole transporting layer, and an electron transporting layer are included as EL layers. An EL element basically has a structure in which an anode, a light emitting layer, and a cathode are laminated in order. In addition to this structure, the EL element may also have a structure in which an anode, a hole injecting layer, a light emitting layer, and a cathode are laminated in order, or a structure in which an anode, a hole injecting layer, a light emitting layer, an electron transporting layer, and a cathode are laminated in order.
Furthermore, an element formed by an anode, an EL layer, and a cathode is referred to as an EL element within this specification.
Circuit operation of an active matrix electronic device is explained next with reference to FIGS. 13A and 13B. First, a voltage is applied to the gate electrode of the switching TFT 1301 when the gate signal line 1305 is selected, and the switching TFT 1301 is placed in a conducting state. The signal (voltage) of the source signal line 1306 is thus stored in the storage capacitor 1304. The voltage of the storage capacitor 1304 becomes a voltage VGS between the gate and the source of the EL driver TFT 1302, and therefore the electric current in response to the storage capacitor 1304 voltage flows in the EL driver TFT 1302 and in the EL element 1303. As a result, the EL element 1303 turns on.
The brightness of the EL element 1303, namely the amount of electric current flowing in the EL element 1303, can be controlled by VGS of the EL driver TFT 1302. VGS is the voltage stored in the storage capacitor 1304, and is the signal (voltage) inputted to the source signal line 1306. In other words, the brightness of the EL element 1303 is controlled by controlling the signal (voltage) of the source signal line 1306. Finally, the gate signal line 1305 is unselected, the gate of the switching TFT 1301 is closed, and the switching TFT 1301 is placed in a non-conducting state. The electric charge stored in the storage capacitor 1304 continues to be stored at this point. VGS of the EL driver 1302 is therefore stored as is, and the electric current in response to VGS continues to flow in the EL driver TFT 1302 and in the EL element 1303.
Information regarding the above explanation is reported upon in papers such as the following: “Current Status and Future of Light-Emitting Polymer Display Driven by poly-Si TFT”. SID99 Digest, p. 372; “High Resolution Light Emitting Polymer Display Driven by Low Temperature Polysilicon Thin Film Transistor with Integrated Driver”, ASIA DISPLAY 98, p. 217; and “3.8 Green OLED with Low Temperature Poly-Si TFT”, Euro Display 99 Late News, p. 27.
Analog gray scale methods and digital gray scale methods exist as methods of gray scale expression for an EL display. In the analog gray scale method, the value of VGS of the EL driver TFT 1302 is changed, the amount of electric current flowing in the EL element 1303 is controlled, and the brightness is changed in an analog manner. In the digital gray scale method, on the other hand, the voltage between the gate and the source of the EL driver TFT operates at only two levels: a range in which no electric current flows in the EL element 1303 (equal to or less than the turn on start voltage); and a range in which the maximum electric current flows (equal to or greater than the brightness saturation voltage). In other words, the EL element 1303 only takes turned-on and turned-off states.
EL displays mainly use the digital gray scale method in which dispersion in characteristics such as the threshold voltage of a TFT does not easily influence display. However, only two-gray-scale display, turned on and turned off, can be performed as is with the digital gray scale method, and therefore plural techniques capable of multiple gray scales by combining the digital gray scale method with another method have been proposed.
One of these techniques is a method in which a surface area gray scale method and a digital gray scale method are combined. The surface area gray scale method is a method of outputting gray scales by controlling the surface area of portions which are switched on. Namely, one pixel is divided into a plurality of sub-pixels, and the number of sub-pixels turned on and the surface area are controlled, and a gray scale is expressed.
FIGS. 14A and 14B are examples of pixel structures for performing gray scale expression in accordance with the surface area gray scale method. A region surrounded by a dotted line frame 1400 in FIG. 14A is a one pixel portion circuit. An enlarged diagram is shown in FIG. 14B. Reference numeral 1401 denotes a first switching TFT, reference numeral 1402 denotes a second switching TFT, reference 1403 denotes a first EL driver TFT, 1404 denotes a second EL driver TFT, 1405 denotes a first EL element, 1406 denotes a second EL element, and reference numeral 1407 is a third EL element. Reference numeral 1408 denotes a first storage capacitor, reference numeral 1409 denotes a second storage capacitor, 1410 denotes a gate signal line, 1411 denotes a first source signal line, 1412 denotes a second source signal line, and reference numeral 1413 is an electric current supply line.
The first switching TFT 1401 and the second switching TFT 1402 are first placed in a conducting state by selecting the gate signal line 1410 in the gray scale expression method. When a signal is not inputted to the source signal line, no EL elements turn on (gray scale 0). When a signal is inputted to the first source signal line 1411, the first EL driver TFT 1403 is placed into a conducting state via the first switching TFT 1401, electric current is supplied to the first EL element 1405, and it turns on. A signal is not inputted to the second source signal line 1412 at this point, and the second EL element 1406 and the third EL element 1407 are in OFF states (gray scale 1). Next, if a signal is inputted to the second source signal line 1412, then the second EL driver TFT 1404 is placed in a conducting state via the second switching TFT 1402, electric current is supplied to the second EL element 1406 and the third EL element 1407, and they turn on. A signal is not inputted to the first source signal line 1411 at this point, and the first EL element 1405 is in a turned-off state (gray scale 2). Finally, when a signal is inputted to both the first source signal line 1411 and the second source signal line 1412, the first EL driver TFT 1403 and the second EL driver TFT 1404 are placed in conducting states via the first switching TFT 1401 and the second switching TFT 1402, electric current is supplied to the first EL element 1405, the second EL element 1406, and the third EL element 1407, and they turn on. All of the EL elements of one pixel turn on at this stage (gray scale 3). Four levels of gray scale expression can thus be performed in the pixel shown in FIGS. 14A and 14B.
Note that, in order to clarify the surface area of the turned on EL elements in FIGS. 14A and 14B, the second and the third EL elements are shown separately, but it is of course also possible to arrange only the second EL element having a surface area equal to twice that of the first EL element.
Disadvantages of this method include fact that it is difficult to increase the resolution, and fact that it is difficult to make a lot of gray scales, because the number of sub-pixels cannot be made large without limits. The surface area gray scale method is reported in papers such as: “TFT-LEPD with Image Uniformity by Area Ratio Gray Scale”. Euro Display 99 Late News, p. 71; and “Technology for Active Matrix Light Emitting Polymer Displays”, IEDM 99, p. 107.
Another method capable of making many gray scales is a method which combines a time gray scale method and a digital gray scale method. The time gray scale method is a method of outputting gray scales by controlling the amount of turn on time. In other words, one frame period is divided into a plurality of subframe periods, and gray scales are expressed by controlling the number and length of the subframe periods turned on.
A case of combining the digital gray scale method, the surface area gray scale method, and the time gray scale method is reported in “Low-Temperature Poly-Si TFT driven Light-Emitting-Polymer Displays and Digital Gray Scale for Uniformity”, IDW'99, p. 171.
FIGS. 15A and 15B are timing charts for a driving method in which digital gray scales and time gray scales are combined. FIG. 15A shows a timing chart for a case in which address (write in) periods and sustain (turn on) periods are completely separated within a subframe period, while a case in which they are not separated is shown in FIG. 15B.
It is normally necessary to form address (write in) periods and sustain (turn on) periods corresponding to the number of bits in a driving method utilizing time gray scales. With a driving method in which the address (write in) periods and sustain (turn on) periods are completely separated (a driving method in which the sustain (turn on) period begins after the address (write in) period of one pixel portion completely finishes in each subframe period), the proportion within one frame period occupied by the address (write in) period becomes large. Further, as shown in FIG. 15A, a period 1501 develops, in which write in and turn on cannot be performed in other rows, during a period in which the gate signal line of a certain row is selected within the address (write in) period. The duty ratio (the length proportion of the sustain (turn on) period within one frame period) is thus greatly reduced. Increasing the operational clock frequency is the only way to shorten the address (write in) period, and considering things such as the circuit operating margin, there are limits to making multiple gray scales. Conversely, with a driving method in which the address (write in) periods and sustain (turn on) periods are not separated, for example, the sustain (turn on) period for the EL element of a number k row, begins immediately after the selection period for the gate signal line of the number k row is completed. Therefore, the pixel is placed in an ON state even during times when the gate signal line is selected by other rows. This is consequently an advantageous driving method for making the duty ratio higher.
Problems such as the following appear, however, when the address (write in) periods and the sustain (turn on) periods are not separated. The length of one address (write in) period is from the start of the selection period for the first row gate signal line until the completion of the selection period of the last row gate signal line. At a certain point, selection of two differing gate signal lines cannot be performed, and therefore it is necessary for the sustain (turn on) period to have a length at least the same as, or greater than, the length of the address (write in) period for a driving method in which the address (write in) periods and sustain (turn on) periods are not separated. The ability to make multiple gray scales is therefore limited by the minimum unit of the sustain (turn on) period. In FIG. 15B, the length of a portion shown by reference numeral 1502, in which a period up through the completion of an address (write in) period Ta4 of the least significant bit portion of a subframe period SF4 does not overlap with a period from the beginning of the first address (write in) period of the next frame period, becomes the minimum unit. Normal display cannot be performed if the sustain (turn on) period has a shorter length. The length of the minimum unit of the sustain (turn on) period Tsmin is expressed by Tsmin=Tan−Tgn if the length of the address (write in) period is taken as Tan and the length of the selection period for one gate signal line is taken as Tgn. The lengths of the sustain (turn on) periods for cases in which the digital gray scale method is combined with the time gray scale method are therefore determined by ratios of powers of 2, and considering the length of one frame period, it becomes difficult to realize multiple gray scales.
A problem in which the minimum unit of the sustain (turn on) period is limited for cases in which the address (write in) period and the sustain (turn on) period are not separated is stated in the above timing charts. The following display method has been proposed in order to resolve this problem.
A sustain (turn on) period Ts3 which is shorter than the minimum unit Tsmin is contained within one frame period, and therefore a portion of Ta3 and a portion of the next frame period Ta1 which starts after the completion of Ts3 are in a state of overlapping in a region denoted by reference numeral 1601 in FIG. 16A. Gate signal lines of differing columns are selected at the same time with this type of overlap portion, and therefore normal scanning cannot be performed. As shown in FIG. 16B, a period 1602 in which the EL element is in a non-display state is then formed in the period in which, the address (write in) period overlaps after the completion of the sustain (turn on) period having a length shorter than the minimum unit Tsmin, and the start timing of the next address (write in) period is delayed. Overlap of the address (write in) period disappears even when sustain (turn on) periods shorter than the minimum unit Tsmin are included, and normal display can consequently be performed.
FIGS. 17A and 17B show pixel structures recorded in Japanese Patent Application No. Hei 11-338786 (applied on Nov. 29, 1999). A range contained within a dotted line frame 1700 in FIG. 17A is one pixel portion. FIG. 17B shows an enlargement diagram of FIG. 17A. Adding to the structure of the pixel shown in FIGS. 13A and 13B, the structures of FIGS. 17A and 17B have a structure in which a reset TFT 1705 and a reset signal line 1712 are added.
Operation of the circuits shown in FIGS. 17A and 17B is explained simply. The operation relating to display of an image is similar to that of a conventional pixel as shown in FIGS. 13A and 13B. The reset TFT 1705 and the reset signal line 1712 are used when forming the above stated non-display periods. The gate voltage applied to the EL driver TFT 1702 in the sustain (turn on) period (the electric potential of the gate electrode of the EL driver TFT 1702 with respect to the source region) is provided in accordance with an electric charge stored by a storage capacitor 1704. Namely, the gate voltage applied to the EL driver TFT 1702 (the electric potential of the gate electrode of the EL driver TFT 1702 with respect to the source region) is equal to the electric potential difference between both terminals of the storage capacitor 1704. A reset signal is inputted to the reset signal line 1712 to make the reset TFT 1705 in a conducting state in order to form the non-display period after the completion of the sustain (turn on) period. The electric potential difference between the source region and the drain region of the reset TFT 1705, namely the electric potential difference between both the terminals of the storage capacitor 1704, becomes 0 V by this operation. The voltage between the gate and the source of the EL driver TFT 1702 therefore becomes 0 V and a non-conducting state is entered. Electric current supply to an EL element 1703 is cut off. The reset TFT 1705 immediately returns to a non-conducting state, but the electric potential difference between both the terminals of the storage capacitor 1704 is maintained as is at 0 V, and therefore the voltage between the gate and the source of the EL driver TFT 1702 also remains at 0 V. The EL element 1703 does not turn on until a new image signal is next written in. The non-display period has at least a length which is found by the equation tr=ta−(ts+tg), where the length of the address (write in) period is taken as ta, the length of the sustain (turn on) period is taken as ts, the length of one gate signal line selection period is taken as tg (with ta, ts, tg>0), and the length of the non-display period is taken as tr (where tr>0). The overlap of the address (write in) periods sandwiching a short sustain (turn on) period can thus be avoided.
However, when using a pixel like that shown in FIGS. 17A and 17B, problems such as the following exist.
As stated above, it is preferable to use a p-channel TFT for the EL driver TFT 1702. The threshold voltage is normally negative when using a p-channel TFT. Consequently, almost no drain current flows when the voltage between the gate and the source of the EL driver TFT 1702 is equal to or greater than 0 V. However, a drain current flows in the EL driver TFT 1702 when passing through the sustain (turn on) period, and therefore this is a condition in which deterioration occurs easily when compared to other TFTs. There are cases in which this varying deterioration and manufacturing irregularities become causes for a shift of the threshold voltage to a positive number. In that case, the drain current flows even if the voltage between the gate and the source is 0 V.
Consider, with reference to FIGS. 17A and 17B, a case in which the threshold voltage of the EL driver TFT 1702 is actually shifted to a positive value. Further, description is given with respect to the period in which a signal is normally written in. When a signal is inputted from a source signal line 1707 and black display (the EL element 1703 does not turn on) is performed, the voltage between the gate and the source of the EL driver TFT 1702 certainly becomes a positive value and the drain current does not flow, provided that the electric potential of the signal inputted from the source signal line 1707 is sufficiently higher than the electric potential of an electric current supply line 1708. In other words, by controlling the signal inputted form the outside normal operation becomes possible even for cases in which TFTs having irregularities such as stated above are included.
On the other hand, with the operation in the non-display period in which the reset TFT 175 is made conductive and the electric current supply to the EL element 1703 is cutoff, the electric potential of the source signal line 1707 and the electric potential of the electric current supply line 1708 become equal in accordance with the reset TFT 1705. The voltage between the gate and the source of the EL driver TFT 1702 becomes 0 V at this time, and a drain current flows if the threshold voltage is shifted to a positive value, and the EL element 1703 emits light. This cannot be handled even if the electric potential of each signal line is changed.